1. Field of the Invention
The invention relates to a cycle time to digital converter, and in particular relates to a cycle time to digital converter with a pulse divider, a decoding circuit and an interface circuit.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional time to digital converter (TDC) 10. Time to digital converter 10 comprises dual delay lock loop (dual DLL) 12, multi phase sampling detector 14 and vernier delay line sampling detector (VDL sampling detector) 15. Dual DLL 12 generates first voltage VBNF and second voltage VBNS according to reference clock signal CLOCK, transmits first voltage VBNF to multi phase sampling detector 14 and VDL sampling detector 15 and transmits second voltage VBNS to VDL sampling detector 15. Multi phase sampling detector 14 receives input signal INPUT, reference clock signal CLOCK and first voltage VBNF to generate digital codes (P0˜Pn−). VDL sampling detector 15 receives input signal INPUT′, first voltage VBNF and second voltage VBNS to generate digital codes (V0˜Vm−).
However, conventional TDC 10 can only detect the time difference between input signal INPUT and reference clock signal CLOCK, but it can't detect high frequency input signal INPUT.